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Selected Recent Publications (under construction)

  • Valeriy Balabanov, Magdalena Widl, and Jie-Hong R. Jiang. QBF Resolution Systems and their Proof Complexities. In Proc. International Conference on Theory and Applications of Satisfiability Testing (SAT'14), Vienna, Austria, July 2014. (pdf)

  • Tai-Yin Chiu, Ruei-Yang Huang, Hui-Ju K. Chiang, Jie-Hong R. Jiang, and Francois Fages. Configurable Linear Control of Biochemical Systems. In Proc. International Workshop on Bio-Design Automation (IWBDA'14), Boston, MA, USA, June 2014. (pdf)

  • Chi-Chuan Chuang, Yi-Hsiang Lai, and Jie-Hong R. Jiang. Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. In Proc. Design Automation Conference (DAC'14), San Francisco, California, USA, June 2014. (pdf)

  • Valeriy Balabanov, Hui-Ju Katherine Chiang, and Jie-Hong R. Jiang. Henkin Quantifiers and Boolean Formulae: A Certification Perspective of DQBF. Theoretical Computer Science (TCS), 523: 86-100, February, 2014. (pdf)

  • Tsung-Po Liu, Shuo-Ren Lin, and Jie-Hong R. Jiang. Software Workarounds for Hardware Errors: Instruction Patch Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 32(12): 1992-2003, December, 2013. (pdf)

  • Yi-Ting Chung and Jie-Hong R. Jiang. Functional Timing Analysis Made Fast and General. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 32(9): 1421-1434, September, 2013. (pdf)

  • Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, and Meng-Yen Li. Encoding Multi-Valued Functions for Symmetry. In Proc. International Conference on Computer-Aided Design (ICCAD'13), San Jose, USA, November 2013. (pdf)

  • Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, and Chien-Mo Li. Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions. In Proc. International Conference on Computer-Aided Design (ICCAD'13), San Jose, USA, November 2013. (pdf)

  • Georg Hofferek, Ashutosh Gupta, Bettina Konighofer, Jie-Hong R. Jiang, and Roderick Bloem. Synthesizing Multiple Boolean Functions Using Interpolation on a Single Proof. In Proc. International Conference on Formal Methods in Computer-Aided Design (FMCAD'13), Portland, USA, October 2013. (pdf)

  • Hui-Ju K. Chiang, and Francois Fages, Jie-Hong R. Jiang, and Sylvain Soliman. On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models. In Proc. International Conference on Computational Methods in Systems Biology (CMSB'13), Klosterneuburg, Austria, September 2013. (pdf)

  • Ruei-Yang Huang, De-An Huang, Hui-Ju K. Chiang, Jie-Hong R. Jiang, and Francois Fages. Species Minimization in Computation with Biochemical Reactions. In Proc. International Workshop on Bio-Design Automation (IWBDA'13), London, UK, July 2013. (pdf)

  • Kuan-Hua Tu and Jie-Hong R. Jiang. Synthesis of Feedback Decoders for Initialized Encoders. In Proc. Design Automation Conference (DAC'13), Austin, Texas, USA, June 2013. (pdf)

  • De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, and Chi-Yun Cheng. Compiling Program Control Flows into Biochemical Reactions. In Proc. International Conference on Computer-Aided Design (ICCAD'12), pages 361-368, San Jose, USA, November 2012. (pdf)

  • Cheng-Shen Han and Jie-Hong R. Jiang. When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way. In Proc. International Conference on Computer Aided Verification (CAV'12), pages 410-426, Berkeley, USA, July 2012. (pdf)

  • Valeriy Balabanov, Hui-Ju K. Chiang and Jie-Hong R. Jiang. Henkin Quantifiers and Boolean Formulae. In Proc. International Conference on Theory and Applications of Satisfiability Testing (SAT'12), pages 129-142, Trento, Italy, June 2012. (pdf)

  • Yi-Ting Chung and Jie-Hong R. Jiang. Functional Timing Analysis Made Fast and General. In Proc. ACM/IEEE Design Automation Conference (DAC'12), pages 1055-1060, San Francisco, USA, June 2012. (pdf)

  • Kuan-Hsien Ho, Xin-Wei Shih, and Jie-Hong R. Jiang. Clock Rescheduling for Timing Engineering Change Orders. In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'12), pages 517-522, Sydney, Australia, January 2012.

  • Kuan-Hsien Ho, Jie-Hong R. Jiang, and Yao-Wen Chang. TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(11): 1723-1733, November, 2012.

  • Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, and Jie-Hong R. Jiang. Automatic Decoder Synthesis: Methods and Case Studies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(9): 1319-1331, September, 2012. (pdf)

  • Valeriy Balabanov and Jie-Hong R. Jiang. Unified QBF Certification and its Applications. Formal Methods in System Design (FMSD), 41(1): 45-65, August 2012. (pdf; final publication available at www.springerlink.com)

  • Alan Mishchenko, Robert Brayton, Jie-Hong R. Jiang, and Stephen Jang. Scalable Don't-Care-Based Logic Optimization and Resynthesis. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4(4):34, December 2011.

  • Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, and Jie-Hong R. Jiang. Towards Completely Automatic Decoder Synthesis. In Proc. IEEE/ACM Int'l Conf. on Computer Aided Design (ICCAD'11), , pages 389-395, San Jose, USA, November 2011. (pdf; ppt)

  • Valeriy Balabanov and Jie-Hong R. Jiang. Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. In Proc. Int'l Conf. on Computer Aided Verification (CAV'11), Salt Lake City, USA, July 2011. (pdf; ResQu released)  <one of 6 top-ranked papers for FMSD inclusion>

  • Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong R. Jiang, Chien-Nan Liu, and Sy-Yen Kuo. Constraint Generation for Software-Based Post-Silicon Bug Repair with Scalable Resynthesis Technique for Constraint Optimization. In Proc. IEEE Int'l Symp. on Quality Electronic Design (ISQED'11), Santa Clara, USA, March 2011.

  • Hsuan-Po Lin, Jie-Hong Roland Jiang, and Ruei-Rung Lee. “Ashenhurst Decomposition Using SAT and Interpolation," in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati (Editors), pages 67-85, Springer, 2011. (book chapter)

  • Ruei-Rung Lee, Jie-Hong Roland Jiang, and Wei-Lun Hung. “Bi-decomposition Using SAT and Interpolation,” in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati (Editors), pages 87-105, Springer, 2011. (book chapter)

  • Jie-Hong Roland Jiang, Hsuan-Po Lin, and Wei-Lun Hung. “Extracting Functions from Boolean Relations Using SAT and Interpolation,” in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati (Editors), pages 287-307, Springer, 2011. (book chapter)

  • Chih-Fan Lai, Jie-Hong R. Jiang, and Kuo-Hua Wang. Boolean Matching of Function Vectors with Strengthened Learning. In Proc. Int'l Conf. on Computer-Aided Design (ICCAD'10), pages 596-601, San Jose, USA, November 2010. (pdf)

  • Bo-Han Wu, Chun-Ju Yang, Chung-Yang (Ric) Huang, and Jie-Hong R. Jiang. A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques. In Proc. Int'l Conf. on Computer-Aided Design (ICCAD'10), pages 729-734, San Jose, USA, November 2010. (pdf)

  • Chih-Fan Lai, Jie-Hong R. Jiang, and Kuo-Hua Wang. BooM: A Decision Procedure for Boolean Matching with Abstraction and Dynamic Learning. In Proc. ACM/IEEE Design Automation Conference (DAC'10), pages 499-504, Anaheim, USA, June 2010. (pdf; ppt) <best paper nominee>

  • Jie-Hong R. Jiang and Tiziano Villa, "Hardware Equivalence and Property Verification," in Boolean Methods and Models in Mathematics, Computer Science and Engineering, Yves Crama  and Peter L. Hammer (Editors), pages 599-674, Cambridge University Press, 2010. (book chapter)

  • Jie-Hong R. Jiang, Chih-Chun Lee, Alan Mishchenko, and Chung-Yang Huang. To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Transactions on Computers, vol. 59, no. 4, pages 457-467, April 2010.

  • Kuan-Hsien Ho, Jie-Hong R. Jiang, and Yao-Wen Chang. TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'10), pages 331-336, Taipei, Taiwan, January 2010.

  • Jie-Hong R. Jiang, Hsuan-Po Lin, and Wei-Lun Hung. Interpolating Functions from Large Boolean Relations. In Proc. Int'l Conf. on Computer-Aided Design (ICCAD'09), pages 779-784, San Jose, USA, November 2009. (pdf; ppt)

  • Natalia Eliseeva, Jie-Hong R. Jiang, Natalia Kushik, and Nina Yevtushenko. Symmetrization in Digital Circuit Optimization. In Proc. IEEE East-West Design & Test Symposium (EWDTS'09), Moscow, Russia, September 2009.

  • Jie-Hong R. Jiang. Quantifier Elimination via Functional Composition. In Proc. Int'l Conf. on Computer Aided Verification (CAV'09), pages 383-397, Grenoble, France, June 2009. (pdf; ppt)

  • Jie-Hong R. Jiang and Srinivas Devadas, “Logic Synthesis in a Nutshell,” in Electronic Deisng Automation: Synthesis, Verification, and Test, Laung-Terng Wang, Kwang-Ting (Tim) Cheng, and Yao-Wen Chang (Editors), pages 299-404, Morgan Kaufmann Publishers, 2009. (book chapter)

  • Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, and Stephen Jang. Scalable don't care based logic optimization and resynthesis. In Proc. ACM International Symposium on Field Programmable Gate Arrays (FPGA'09), pages 151-160, Monterey, California, USA, February 2009. (pdf)

  • Hsuan-Po Lin, Jie-Hong R. Jiang, and Ruei-Rung Lee. To SAT or Not to SAT: Ashenhurst Decomposition in a Large Scale. In Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'08), pages 32-37, San Jose, USA, November 2008. (pdf; ppt)

  • Sz-Cheng Huang and Jie-Hong R. Jiang. A Dynamic Accuracy-Refinement Approach to Timing-Driven Technology Mapping. In Proc. IEEE Int'l Conf. on Computer Design (ICCD'08), pages 538-543, Lake Tahoe, USA, October 2008. (pdf)

  • Ruei-Rung Lee, Jie-Hong R. Jiang, and Wei-Lun Hung. Bi-Decomposing Large Boolean Functions via Interpolation and Satisfiability Solving. In Proc. ACM/IEEE Design Automation Conference (DAC'08), pages 636-641, Anaheim, USA, June 2008. (pdf; ppt)

  • Jie-Hong R. Jiang, Dah-Wei Chiou, and Cheng-En Wu. Quantum Mechanical Search and Harmonic Perturbation. Quantum Information Processing, vol. 6, issue 5, pages 349-362, October 2007. (pdf)

  • Jie-Hong R. Jiang and Wei-Lun Hung. Inductive Equivalence Checking under Retiming and Resynthesis. In Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07), pages 326-333, San Jose, USA, November 2007. (pdf)

  • Chih-Chun Lee, Jie-Hong R. Jiang, Chung-Yang (Ric) Huang, and Alan Mishchenko. Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving. In Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07), pages 227-233, San Jose, USA, November 2007. (pdf) <best paper nominee>

  • Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong R. Jiang, and Yao-Wen Chang. A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. In Proc. Int'l Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'07), pages 148-159, Göteborg, Sweden, September 2007. (pdf)

  • Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, and Stephen Jang. SAT-based Logic Optimization and Resynthesis. In Proc. Int'l Workshop on Logic Synthesis (IWLS'07), pages 358-364, San Diego, USA, May 2007. (pdf)

  • Jie-Hong R. Jiang, Dah-Wei Chiou, and Cheng-En Wu. Quantum Mechanical Search and Harmonic Perturbation. quant-ph/0702007, February 2007. (pdf)

  • Jie-Hong R. Jiang and Robert K. Brayton. Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pages 2674-2686, December 2006. (pdf)

    (A preliminary version of this work was presented in part as:
    Jie-Hong R. Jiang. On Some Transformation Invariants under Retiming and Resynthesis. In Proc. Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'05), pages 413-428, Edinburgh, UK, April 2005. (pdf))

　

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　 Conference Submission Deadline Conference Period
　
July
January
　 FPGA September February
　
October
March
　
September
March
　
November
June
　
March
June
　 SAT February June
　
January
June
　
January
July
　 ICCD May October
　 FMCAD May October
　
April
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